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TRIPATH Technology, Inc. - Preliminary Technical Information
TCD6000 6 CHANNEL CLASS-T DIGITAL AUDIO PROCESSOR USING DIGITAL POWER PROCESSINGTM TECHNOLOGY
Technical Information - Preliminary Revision 1.0 - September 2004
General Description
The TCD6000 is a high-performance 6-channel digital audio amplifier processor. It receives 6 digital audio channels (3 pairs) and outputs 6 complementary single-bit digital data streams suitable for driving TRIPATH or other switching output stages. The TCD6000 accepts data at audio sample rates ranging from 32kHz to 192kHz and incorporates digital interpolation and sigma-delta conversion to produce streamed digital output signals. When combined with switching output stages, the TCD6000 allows the implementation of a complete digital audio system incorporating Class-T Digital Audio Amplification.
Features
Class-T architecture combining ultra-low distortion with high efficiency Inputs support I2S and other PCM audio formats Up to 24-bit resolution (16, 18, 20, and 24 bit) 104dB dynamic range THD+N less than 0.03% Input sampling rates up to 192kHz I2C compatible interface Stereo headphone amplifier Predictive Gain Control Digital volume control 128dB range 1/2 dB step size in 1/8 dB increments Zero crossing detection for click free transitions Optional mute mode leaves headphone amplifiers operating Automatic DC offset cancellation 130uV noise floor (PGC = 1/8, low post gain) Digital de-emphasis filtering for 32, 44.1 and 48kHz sampling rates
Digital Filter Engine Channel 1 & 2 Serial Input Data Port Channel 3 & 4 Channel 5 & 6 BITCK LRCK MCK Digital Filter Engine Reference Voltages Digital Filter Engine Digital Filter Engine Digital Filter Engine Digital Filter Engine
Class-T Signal Processor Class-T Signal Processor Class-T Signal Processor Class-T Signal Processor Class-T Signal Processor Class-T Signal Processor
Y1/B FB1P/N HP1 Y2/B FB2P/N HP2 Y3/B FB3P/N Y4/B FB4P/N Y5/B FB5P/N Y6/B FB6P/N
I2C Port
Control Signals
VCLAMP
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TCD6000 - Rev. 1.0/09.04
OVRLDB
REXT
SCK
SDA
VD18EN
RESETB
HMUTE
V2BG
FAULT
TST_EN
TRIPATH Technology, Inc. - Preliminary Technical Information
Absolute Maximum Ratings
SYMBOL VD33 VA33 VA50 Vlogic3 Vin5 TA TSTORE TJMAX ESDHB ESDMM PARAMETER 3.3V Digital Power Supply 3.3V Analog Power Supply 5V Analog Power Supply Input Logic Level (DATAx, MCK, BITCLK, LRCLK, SCK, SDA, RESET, ADDRx) Input Level (VCLAMP, FBxx, FAULT) Operating Free-air Temperature Range Storage Temperature Range Maximum Junction Temperature ESD Susceptibility - Human Body Model (Note 2) All pins ESD Susceptibility - Machine Model (Note 3) All pins Min -0.3 -0.3 -0.3 -0.3 -0.3 -40 -55 Max 4.0 4.0 6.0 VD33+0.3 VD50+0.3 85 150 150 2000 200 C C C V V UNITS V V V V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. See the table below for Operating Conditions. Note 2: Human body model, 100pF discharged through a 1.5K resistor. Note 3: Machine model, 220pF - 240pF discharged through all pins.
Recommended Operating Conditions (Note 4)
SYMBOL VA50 VA33 VD33 VHI-3 VLO-3 TA PARAMETER 5V Analog Power Supply 3.3V Analog Power Supply 3.3V Digital Power Supply Vlogic3 Input High Vlogic3 Input Low Operating Temperature Range MIN 4.5 3.0 3.0 2.1 0 -40 25 TYP 5 3.3 3.3 MAX 5.5 3.6 3.6 VD33 0.8 85 UNITS V V V V V C
Note 4: Recommended Operating Conditions indicate conditions for which the device is functional. See Digital, Analog, and Switching Characteristics for guaranteed specific performance limits.
Power and Thermal Characteristics
TA = 25 C. See Application/Test Circuit on page 8.
SYMBOL PARAMETER PTOTAL Total Power Dissipation IA50 IA33 ID33 I33 JA VA50 Power Supply Current VA33 Power Supply Current VD33 Power Supply Current CONDITIONS VA50 = 5.0V VA33 = 3.3V VD33 = 3.3V VA50 = 5.0V VA33 = 3.3V VD33 = 3.3V MIN TYP 880 65 50 20 100 35 90 MAX UNITS mW mA mA mA mA C/W
Combined VD33+VA33 Power Supply VD33 = 3.3V Current (Note 5) VA33 = 3.3V Junction-to-ambient Thermal Resistance (still air)
Note 5: Separate IA33 and ID33 maximums are not tested.
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Digital Characteristics
TA = 25 C. Unless otherwise noted, the MCK frequency is 12.288. See Application/Test Circuit on page 8.
SYMBOL PARAMETER VIH33 High-Level Input Voltage VIL33 FAULTIH5 FAULTIL5 VOH33 VOH5 VOL33 VOL5 Low-Level Input Voltage FAULT High-Level Input Voltage FAULT Low-Level Input Voltage High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Low-Level Output Voltage CONDITIONS VD33 = 3.3V VD33 = 3.3V VA50 = 5.0V VA50 = 5.0V VA50 = 5.0V VD33 = 3.0V, IOL = -50uA VD33 = 3.0V, IOL = -4mA VA50 = 4.5V, IOL = -50uA VA50 = 4.5V, IOL = -8mA VD33 = 3.0V, IOL = 50uA VD33 = 3.0V, IOL = 4mA VA50 = 4.5V, IOL = 50uA VA50 = 4.5V, IOL = 8mA 2 2.9 2.48 4.4 3.8 0.1 0.44 0.1 0.44 3.5 0.8 3 MIN 2.1 TYP MAX 0.8 UNITS V V V V V V V V V V V V V
FAULTOFF FAULT Off Input Voltage
Performance Characteristics
TA = 25 C. Unless otherwise noted, the power stage used for testing is the TP2150B, the supply voltage is VPP=|VNN|=28V, RL = 4, PGC = 1, post-gain = high, the MCK frequency is 12.288 MHz, fs = 48kHz, the input frequency is 1kHz, and the measurement bandwidth is 20kHz. See Application/Test Circuit on page 8.
SYMBOL PARAMETER POUT Output Power (continuous RMS/Channel) THD + N IHF-IM SNR CS AVERROR eNOUT
CONDITIONS THD+N = 0.1% THD+N = 1.0% THD+N = 10% Total Harmonic Distortion Plus Noise POUT = 20W/Channel 19kHz, 20kHz, 1:1 (IHF), POUT = 10W/Channel PGC = 1, post-gain = high, A Weighted, POUT = 100W/Channel 0dBr = 10W Pout = 100W/Channel POUT = 10W/Channel PGC = 1, post-gain = high PGC = 1/8, post-gain = high PGC = 1/8, post-gain = low After automatic DC calibration
MIN
TYP MAX UNITS 60 W 75 W 105 W 0.03 % -80 98 84 87 0.2 260 150 130 40 dB dB dB % dB V V V mV
IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Power Efficiency Channel to Channel Gain Error Output Noise Voltage (A-Weighted) Output Offset Voltage
VOFFSET
-95
+95
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TRIPATH Technology, Inc. - Preliminary Technical Information
Switching Characteristics
TA = 25 C. Unless otherwise noted, the MCK frequency is 12.288 MHz and the measurement bandwidth is 20kHz. See Application/Test Circuit on page 8.
SYMBOL
fMCK
PARAMETER Master Clock Timing Frequency Duty Cycle
CONDITIONS
MIN
TYP
MAX
UNITS
8.192 40
24.56 60
MHz %
fLRCK
Left-Right Clock Timing 1X Mode 2X Mode 4X Mode Serial Interface Timing BITCK period 1X Mode 2X Mode 4X Mode Control Interface Timing SCK Period SCK Pulse Width Low SCK Pulse Width High SDA Setup Time SDA Hold Time SDA Rise Time SDA Fall Time
32
44.1 96 192
48
KHz KHz kHz
tBITCK
488.2
354.3 177.1 88.6
325.5
ns ns ns
tSCK tSCKL tSCKH tSDAset tSDAhold tSDA rise tSDAfall
200 80 80 40 40 20 20
ns ns ns ns ns ns ns
LRCK
BITCLK
DATA
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TCD6000 Pin Layout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82 VD33
V2BG
REXT
VA50
VA33
VCLAMP
V2BGFILT
FB1P
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VD18CAP
FB1N
TEST
GA
GA
GA
HP2
HP1
GA
GD
NC
NC
81
FB2P GA FB2N NC NC NC FB3N FB3P FAULT FB4N FB4P HMUTE FB5N FB5P TST_EN FB6N FB6P NC OVRLDB Y1 Y1B Y2 Y2B NC NC NC NC NC GA Y3 VD18CAP
TEST TEST NC NC GA GD ADDR1 TEST ADDR2 TESTMODE RESETB VD18EN LRCK BITCK DATA56 DATA34 DATA12 SDA SCK MCK GD TEST TEST GA GA NC NC NC NC TEST
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
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50
VD33
VA50
VA33
VA33
Y3B
Y4B
Y5B
Y6B
GD
GA
GA
GA
GA
NC
NC
NC
Y4
Y5
Y6
TRIPATH Technology, Inc. - Preliminary Technical Information
TCD6000 Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Function FB2P GA FB2N NC NC NC FB3N FB3P FAULT FB4N FB4P HMUTE FB5N FB5P TST_EN FB6N FB6P NC OVRLDB Y1 Y1B Y2 Y2B NC NC NC NC NC GA Y3 Y3B Y4 Y4B VA50 GA Y5 Y5B Y6 Y6B NC NC GA VA33 VA33 NC GA GA GD VD18CAP VD33 TEST NC NC NC NC GA GA TEST TEST GD MCK SCK SDA Type Input Ground Input Not connected internally Not connected internally Not connected internally Input Input Input Input Input 5V Logic Output Input Input 5V Logic Output Input Input Not connected internally 5V Logic Output 5V Logic Output 5V Logic Output 5V Logic Output 5V Logic Output Not connected internally Not connected internally Not connected internally Not connected internally Not connected internally Ground 5V Logic Output 5V Logic Output 5V Logic Output 5V Logic Output Power Ground 5V Logic Output 5V Logic Output 5V Logic Output 5V Logic Output Not connected internally Not connected internally Ground Power Power Not connected internally Ground Ground Ground Output Power Float Not connected internally Not connected internally Not connected internally Not connected internally Power Power Float Float Ground 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input Description Switching feedback Analog Ground Switching feedback must be kept floating must be kept floating must be kept floating Switching feedback Switching feedback 3-level digital input to detect power stage fault condition Switching feedback Switching feedback Digital output - indicates processor channels are muted Switching feedback Switching feedback Digital output to put power stage in to test mode Switching feedback Switching feedback must be kept floating Digital output - indicates that one or more channels are near saturation Switching modulator output Switching modulator output Switching modulator output Switching modulator output must be kept floating must be kept floating must be kept floating must be kept floating must be kept floating Analog Ground Switching modulator output Switching modulator output Switching modulator output Switching modulator output 5V analog power supply Analog ground Switching modulator output Switching modulator output Switching modulator output Switching modulator output must be kept floating must be kept floating Analog ground 3.3V analog power supply 3.3V analog power supply must be kept floating Analog ground Analog ground Digital Ground Decoupling point for internal 1.8V regulator 3.3V digital power supply Test pin - must be kept floating must be kept floating must be kept floating must be kept floating must be kept floating Analog ground Analog ground Test pin - must be kept floating Test pin - must be kept floating Digital ground Master clock digital input 2 I C clock input 2 I C serial data input
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TRIPATH Technology, Inc. - Preliminary Technical Information 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DATA12 DATA34 DATA56 BITCK LRCK VD18EN RESETB TESTMODE ADDR2 TEST ADDR1 GD GA NC NC TEST TEST TEST VD33 VD18CAP GD GA GA REXT V2BGFILT VA33 GA NC NC V2BG HP1 HP2 GA VA50 FB1P FB1N VCLAMP 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input 3.3V Logic Input Float 3.3V Logic Input Ground Ground Not connected internally Not connected internally Float Float Float Power Output Ground Ground Ground Output Output Power Ground Not connected internally Not connected internally Output Output Output Ground Power 5V Logic Output 5V Logic Output Input PCM audio input for channels 1 and 2 PCM audio input for channels 3 and 4 PCM audio input for channels 5 and 6 PCM audio bit clock input PCM audio left/right clock input 1.8V internal regulator enable Reset input - resets internal registers Test mode enable - must be kept grounded Chip address select 2 Test pin - must be kept floating Chip address select 1 Digital ground Analog ground must be kept floating must be kept floating Test pin - must be kept floating Test pin - must be kept floating Test pin - must be kept floating 3.3V digital power supply Decoupling point for internal 1.8V regulator Digital ground Analog ground Analog ground Analog current reference input - requires 10K ohms +/- 1% to GA Reference Voltage 3.3V analog power supply Analog ground must be kept floating must be kept floating Reference Voltage Headphone amplifier output channel 1 Headphone amplifier output channel 2 Analog ground 5V analog power supply Switching feedback Switching feedback Soft clamp threshold voltage input to control audio signal clipping
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TCD6000 Connection Diagram
4 5 6 18 24 25 26 27 28 40 41 45 52 53 54 55 77 78 91 92 5V VA50 GA 34 35 Cs 0.1uF
3.3V Cs 0.1uF Cs 0.1uF 3.3V Cs 0.1uF Cs 0.1uF 82 83 75 48 84 56 Rp Rp 3.3V 69 2-WIRE CONTROL 62 63 VD33 50 49 60 VD33
VD18CAP GD
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
5V VA50 GA Y1 Y1B FB1P FB1N Y2 Y2B FB2P FB2N Y3 Y3B FB3P FB3N Y4 Y4B FB4P FB4N Y5 Y5B FB5P FB5N Y6 Y6B FB6P FB6N 97 96 20 21 98 99 22 23 1 3 30 31 8 7 32 33 11 10 36 37 14 13 38 39 17 16 Ch 100u;10V Cs 0.1uF
VD18CAP GD GD GD GA
POWER STAGE AND FEEDBACK
3.3V
POWER STAGE AND FEEDBACK
VD18EN SCK SDA
POWER STAGE AND FEEDBACK
ADDRESS
74 72 61 68 67 64 65 66 70 3.3V Cs 0.1uF 43 46
ADDR1 ADDR2 MCK LRCK BITCK DATA12 DATA34 DATA56 RESETB VA33 GA
POWER STAGE AND FEEDBACK
PCM AUDIO SOURCE
POWER STAGE AND FEEDBACK
RESET
POWER STAGE AND FEEDBACK
HP1 HP2
94 95
Cs 0.1uF
89 86
VA33 GA
10 0.1uF
10 0.1uF
100u;10V Ch VPP 5V
+
3.3V
2 3 4 5 1
+
5V Rd
5V
Cv2bg 0.1uF
88
V2BGFILT VCLAMP 100 0.1uF OVRLDB TST_EN HMUTE FAULT 19 15 12 9 93 Cv2bg 0.1uF TEST TEST TEST TEST TEST TEST TEST FAULT DETECT 4.7uF Ra
QB
QA
85
+
Rb Ra
GA
3.3V Cs 0.1uF 44 VA33
VNN
47
GA
V2BG
71
GA GA GA GA GA GA
TESTMODE
REXT
87 Rext 10K 1%
2 29 42 57 76 90
Connect ground planes at a single location near TCD6000.
8
51 58 59 73 79 80 81
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TRIPATH Technology, Inc. - Preliminary Technical Information
TCD6000 Operation Overview
POWER SUPPLY The TCD6000 requires both 3.3V and 5V supplies. Pins labeled VD33 correspond to the digital power networks, and pins labeled VA33 and VA50 correspond to the analog power networks. All should be separately decoupled to their respective grounds. All TCD6000 logic inputs are 3.3V unless otherwise specified. VD18EN VD18EN is a logic input that enables the internal 1.8V regulator. It should be tied to VD33. REXT The REXT pin should be connected to ground through an external 10K. This connection is used by the TCD6000 as a current reference. The 10K resistor must have an accuracy of +/- 1%. V2BG and V2BGFILT The V2BG and V2BGFILT pin should each be AC coupled to GA with a 0.1uF capacitor. RESETB When pulled low, the RESETB pin will force all control registers from sub-address 00h to 6Fh and 80h to EFh to their default state. Registers from sub-address 70h to 7Fh and F0h to FFh remain unchanged. FAULT The TCD6000 has no fault detection circuitry of its own. Over/under voltage, over current, and over temperature fault detection are expected to be done externally. However, a FAULT input has been provided as an alternate "mute" input. The default (non-muted) state for FAULT is "floating". The pin will self-bias to approximately 2.5V. If FAULT is taken to either 5V or 0V the TCD6000 will go in to hard mute. If FLD (register 3Ah bit D2) is set to `1', the TCD6000 will automatically un-mute after FAULT is released (forced or floated back to 2.5V). If FLD is cleared to `0', the TCD6000 will remain latched in this FAULT-based muted condition until the FAULT pin is released and FLC (register 3Ah bit D1) undergoes a `0' to `1' transition. AUTOMATIC DC OFFSET CALIBRATION When the TCD6000 comes out of hard mute (register 2Ch bit D1 transitions from `1' to `0') an automatic DC offset calibration sequence is started. During this sequence, the TCD6000 calibrates itself and its external components to minimize DC offset at the speaker outputs that can be caused by process variations and component tolerance. The automatic DC offset calibration sequence takes a maximum of 1 second if the PGC is disabled and 4 seconds if the PGC is enabled. The additional time is required because each different amplifier gain level may require a different calibration level. Therefore, each of the four PGC levels will require calibration upon un-muting. Automatic DC offset calibration produces 10 bit offset values for each channel that are stored in internal registers. When Automatic DC offset calibration is enabled, the 10 bit values that are in use can be read in the Calibration Readback registers (registers 02h - 09h). When the PGC is enabled, four different values are stored for each channel. The values that are seen in the Calibration Readback registers will change as the PGC Setting changes.
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PREDICTIVE GAIN CONTROL The Predictive Gain Control (PGC) automatically sets one of four different pre-gain levels depending on the Channel Volume level (registers 25h - 2Ah). The PGC allows less gain to be used for lower volume levels. This results in greater digital resolution and lower noise floor. When PGC is enabled (register 3Dh bit D7 is set to `1'), PGC settings are changed automatically by the Channel Volume. When PGC is disabled, the system's pre-gain level is always set to full gain.
Channel Volume Range FFh - F4h F3h - E8h E7h - DCh DBh - 00h PGC Setting Full Gain 1/2 Gain 1/4 Gain 1/8 Gain
POST-GAIN When the GNn control bits are cleared to `0', the TCD6000 operates in low post-gain mode. In this mode, the noise floor is lowered but the system may not be able to obtain the maximum power output from the power stage. When the GNn control bits are set to `1', the TCD6000 operates in high post-gain mode. In this mode, gain is increased by 25% (about 2dB). The system will now be able to obtain the maximum power output from the power stage but the noise floor will have increased accordingly. The user may use low post-gain at low volume levels to take advantage of the lower noise floor and use high post-gain at higher volume levels to take advantage of the full range of the power stage. Precautions must be taken while changing post-gain to prevent DC offset. The automatic DC offset cancellation settings will have been affected by changes in post-gain. To avoid this problem, the software that is controlling the TCD6000 through the I2C port should store DC calibration values for each post-gain setting and swap between them as in the following procedure: 1. 2. 3. 4. 5. 6. 7. Set post-gain to low and channel volumes to 00h. Un-mute. Wait for calibration to complete. Read values in the "Calibration Readback" registers and write them to the "Calibration Bank" registers. Mute. Set post-gain to high and channel volumes to 00h. Un-mute.
Now the calibration bank contains the DC calibration values for low post-gain and the TCD6000 has stored the DC calibration values for high post-gain in its internal registers. When the CFn bits (register 2Fh bits D5..D0) are set to `1', the values stored in the Calibration Bank are used. When the CFn bits are cleared to `0', the internal registers that hold the automatic DC calibration values for high post-gain are used. If the PGC is enabled, the software should only switch between low and high post-gain modes when the PGC is in 1/8 Gain mode. This is because the values stored in the Calibration Bank will only be valid for the PGC mode that was in effect when the channel volumes were set to 00h and automatic DC calibration took place. Special care should be taken when using this scheme to prevent events from interfering with DC calibration. FAULT should be latched so that a proper calibration can take place during un-mute. Clocks should be kept synchronized to prevent Sync Reset. I C INTERFACE The I2C interface is a simple bi-directional bus interface for allowing a microcontroller to read and write 2 control registers in the TCD6000. Every component hooked up to the I C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and/or transmitter depending on its functionality. The TCD6000 acts as a slave while a microcontroller would act as a master. The TCD6000 device address is 80h, 82h, 84h, or 86h depending on the state of the ADDRn pins. The TCD6000 constantly monitors the I2C data input and waits until its device address appears before writing into or reading from its control registers. The 8th bit of the address determines whether the master is reading 10 TCD6000 - Rev. 1.0/09.04
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TRIPATH Technology, Inc. - Preliminary Technical Information
or writing. When the last bit is HIGH, the master is reading from a register on the slave. When the last bit is LOW, the master is writing to a register on the slave. ADDR2 0 0 1 1 ADDR1 0 1 0 1 TCD6000 write address 80h 82h 84h 86h TCD6000 read address 81h 83h 85h 87h
The I2C interface consists of a serial data input (SDA) and a clock input (SCK) and is capable of both reading and writing. Both SCK and SDA are bidirectional lines connected to VD33 via a pull-up resistor. When the bus is free both lines are HIGH. The SCK clock frequency is typically less than 400 kHz. Data is transmitted serially in groups of 8 bits, followed by an acknowledge bit. The data on the SDA line is expected to be stable while SCK is HIGH.
SCK
SDA
A7
A6
A5
A4
A3
A2
A1
R/W
D7
D6
D5
D4
D3
D2
D1
D0
start
ACK
ACK
stop
A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. Data transfer with acknowledge is obligatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The receiver can hold the SCK line LOW after an acknowledge to force the transmitter to wait until the receiver is ready to accept another byte. When addressed as a slave, the following protocol must be adhered to, once a slave acknowledge has been returned, an 8-bit sub-address will be transmitted. If the LSB of the slave address was `1', a repeated START condition will have to be issued after the address byte; if the LSB is `0' the master will transmit to the slave with direction unchanged. When the master writes data to the slave, the following events occur: SDA and SCK are both HIGH. A start condition is generated when the master pulls SDA LOW. The master begins toggling SCK and transmits the slave's device address on SDA with a 0 in the LSB (ex. 80h). 3. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA LOW. 4. The slave holds SCK low until it is ready to receive the next byte. 5. The slave releases SCK and the master begins toggling SCK and transmits the control register address on SDA. 6. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA LOW. 7. The slave holds SCK low until it is ready to receive the next byte. 8. The slave releases SCK and the master begins toggling SCK and transmits the data byte on SDA. 9. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA LOW. 10. The slave holds SCK low until it is ready to receive the next byte. 11. To transmit additional data bytes, repeat steps 8 through 10. 12. A stop condition is generated when SCK is released and SDA goes HIGH while SCK is still high. 0. 1. 2.
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When the master reads data from the slave, the following events occur: SDA and SCK are both HIGH. A start condition is generated when the master pulls SDA LOW. The master begins toggling SCK and transmits the slave's device address on SDA with a 1 in the LSB (ex. 81h). 3. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA LOW. 4. The slave holds SCK low until it is ready to receive the next byte. 5. The slave releases SCK and the master begins toggling SCK and transmits the control register address on SDA. 6. On the ninth SCK pulse, the master releases SDA and the slave acknowledges by pulling SDA LOW. 7. The slave holds SCK low until it is ready to transmit data. 8. The slave releases SCK and the master begins toggling SCK and the slave transmits the data byte on SDA. 9. On the ninth SCK pulse, the slave releases SDA and the master acknowledges by pulling SDA LOW. 10. The slave holds SCK low until it is ready to transmit the next byte. 11. To read additional data bytes, repeat steps 8 through 10. 12. A stop condition is generated when SCK is released and SDA goes HIGH while SCK is still high. When writing to the TCD6000, the first data byte after the device address is a sub-address. Subsequent data will be written to TCD6000 control registers referred to by the sub-address. When reading from the TCD6000, data will be read starting from the most recently written sub-address. Control registers from sub-addresses 00h through 7Fh can also be accessed at sub-addresses 80h through FFh. The difference is that sub-addresses 80h through FFh are auto-increment registers. Repeated reads and writes to these registers will automatically increment the sub-address. For example, if a microcontroller wanted to write a value of E6h to all of the volume registers, it would write the following bytes through its I2C port: 80h A5h E6h E6h E6h E6h E6h E6h . If it wanted to read those values back it would send: 80h A5h 81h . 0. 1. 2.
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Control Registers
This section describes the user-programmable registers controlling many features of the TCD6000. They are 2 programmed using the I C interface. Control bits shown in gray are for TRIPATH use only and should be set to the values shown. All registers not shown are reserved and should not be changed. Control Register Mapping
Sub-Addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h Register Name Mute Status Volume Status Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Freeze Control Filter Bypass Control Sampling Rate Control Operation Control Digital Input Format Channel 1 Volume Channel 2 Volume Channel 3 Volume Channel 4 Volume Channel 5 Volume Channel 6 Volume Volume Ramp Rate Channel Mute Control Auto-Mute Timing Volume Change Control DC Calibration Control Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Force DC Dither Control D7 0 0 CR19 CR29 CR39 0 CR49 CR59 CR69 0 0 DCB 0 0 0 V17 V27 V37 V47 V57 V67 RR7 M6 AM7 0 0 CB19 CB29 CB39 0 CB49 CB59 CB69 0 FD7 DT7 D6 0 0 CR18 CR28 CR38 0 CR48 CR58 CR68 0 0 DEB 0 1 DP V16 V26 V36 V46 V56 V66 RR6 M5 AM6 0 CAB CB18 CB28 CB38 0 CB48 CB58 CB68 0 FD6 DT6 D5 0 VZ6 CR17 CR27 CR37 CR31 CR47 CR57 CR67 CR61 0 DRB 0 0 BCK V15 V25 V35 V45 V55 V65 RR5 M4 AM5 0 CF6 CB17 CB27 CB37 CB31 CB47 CB57 CB67 CB61 FD5 DT5 D4 MUS VZ5 CR16 CR26 CR36 CR30 CR46 CR56 CR66 CR60 0 0 1Xf 0 CCK V14 V24 V34 V44 V54 V64 RR4 M3 AM4 0 CF5 CB16 CB26 CB36 CB30 CB46 CB56 CB66 CB60 FD4 DT4 D3 SMU VZ4 CR15 CR25 CR35 CR21 CR45 CR55 CR65 CR51 0 0 1Xs HFR I2S V13 V23 V33 V43 V53 V63 RR3 M2 AM3 VR1 CF4 CB15 CB25 CB35 CB21 CB45 CB55 CB65 CB51 FD3 DT3 D2 FMU VZ3 CR14 CR24 CR34 CR20 CR44 CR54 CR64 CR50 0 0 0 0 DA V12 V22 V32 V42 V52 V62 RR2 M1 AM2 VR0 CF3 CB14 CB24 CB34 CB20 CB44 CB54 CB64 CB50 FD2 DT2 D1 HMU VZ2 CR13 CR23 CR33 CR11 CR43 CR53 CR63 CR41 0 0 S4X R1 DW1 V11 V21 V31 V41 V51 V61 RR1 HM AM1 VRE CF2 CB13 CB23 CB33 CB11 CB43 CB53 CB63 CB41 FD1 DT1 D0 AMU VZ1 CR12 CR22 CR32 CR10 CR42 CR52 CR62 CR40 CHG 0 S2X R0 DW0 V10 V20 V30 V40 V50 V60 RR0 AM AM0 ZCE CF1 CB12 CB22 CB32 CB10 CB42 CB52 CB62 CB40 FD0 DT0
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TRIPATH Technology, Inc. - Preliminary Technical Information 3Ah 3Bh 3Ch 3Dh 73h 74h 75h 76h 77h 78h 7Ah 7Bh 7Dh Fault Latch Control Saturation Clamp LSB Saturation Clamp MSB Predictive Gain Control Output Delay Control Headphone and Logic Test Output Timing Control Individual Hard Mute Gain Control Gain Control Gain Control B Cal Control 0 1 1 PGC 0 0 0 DEL 0 GN1 GN2 GN6 0 0 1 1 0 0 HMP 0 DCB HM6 0 0 GN5 BC6 0 1 1 0 YSGL HPO 0 0 HM5 0 0 GN4 BC5 0 1 0 0 0 TO 0 0 HM4 0 0 GN3 BC4 0 1 0 0 YD3 0 0 STB HM3 0 0 0 BC3 FLD 1 1 0 YD2 0 0 BB2 HM2 0 0 0 BC2 FLC 1 1 0 YD1 0 0 BB1 HM1 0 0 0 BC1 0 1 1 0 YD0 0 0 BB0 0 0 0 0 0
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Mute Status
Addr 00h Register Name Mute Status Default D7 0 0 D6 0 0 D5 0 0 D4 MUS 0 D3 SMU 0 D2 FMU 0 D1 HMU 0 D0 AMU 0
This is a read only register that indicates the status of various mute conditions. A `1' indicates that that particular mute is active. AMU = Auto Mute HMU = Hard Mute FMU = Fault Mute SMU = Sync Mute MUS is the logical OR of D3..D1. If any of the above mute states are active, MUS will be set to `1'. Volume Status
Addr 01h Register Name Volume Status Default D7 0 0 D6 0 0 D5 VZ6 0 D4 VZ5 0 D3 VZ4 0 D2 VZ3 0 D1 VZ2 0 D0 VZ1 0
These are read only bits that are set to `1' when their respective volume registers are cleared to 0. For example, when register 27h has a value of 8Ch, VZ3 is cleared to `0'. When register 27h has a value of 00h, VZ3 is set to `1'. Calibration Readback
Addr 02h 03h 04h 05h 06h 07h 08h 09h Register Name Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Calibration Readback Default D7 CR19 CR29 CR39 0 CR49 CR59 CR69 0 0 D6 CR18 CR28 CR38 0 CR48 CR58 CR68 0 0 D5 CR17 CR27 CR37 CR31 CR47 CR57 CR67 CR61 0 D4 CR16 CR26 CR36 CR30 CR46 CR56 CR66 CR60 0 D3 CR15 CR25 CR35 CR21 CR45 CR55 CR65 CR51 0 D2 CR14 CR24 CR34 CR20 CR44 CR54 CR64 CR50 0 D1 CR13 CR23 CR33 CR11 CR43 CR53 CR63 CR41 0 D0 CR12 CR22 CR32 CR10 CR42 CR52 CR62 CR40 0
These read only registers show the current automatic DC calibration values. The DC calibration values are 10 bit words so they are stored in separate bytes. For example, for channel 1, the 8 most significant bits are stored in register 02h, while the 2 least significant bits are stored in register 05h - bits D1 and D0. When PGC is enabled, four different automatic DC calibration values are stored internally - one for each PGC setting. As the channel volume is changed across PGC boundaries, the Calibration Readback value will change to reflect the new PGC setting. For example, if the user changes channel 1 volume from FFh down to F0h, the PGC level has changed from "full" down to "1/2". Internally, the TCD6000 switches from the DC calibration value that it calculated for full PGC to the DC calibration value that it calculated for 1/2 PGC. The value present in the channel 1 Calibration Readback register also changes to indicate the 1/2 PGC DC calibration value. Freeze Control
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TRIPATH Technology, Inc. - Preliminary Technical Information Addr 20h Register Name Freeze Control Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 CHG 0
While CHG is set to `1', any value that is written to a register takes effect immediately. However, while CHG is cleared to `0', any changes that are made to registers 00h through 6Fh and 80h through EFh will not take effect until CHG is set to `1'. For example, if the user wanted to set all channels to a volume of F6h at the same time, the user could clear CHG, set registers 25h through 2Ah to F6h one at a time, then set CHG to `1'. Registers 70h through 7Fh and F0h through FFh are not affected by CHG. Filter Bypass Control
Addr 21h Register Name Filter Bypass Control Default D7 DCB 0 D6 DEB 0 D5 DRB 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
This register allows users to bypass any of the 3 digital filters incorporated in the TCD6000: DCB = DC blocking filter DEB = De-Emphasis filter DRB = Droop correction filter Setting these bits to `1' bypasses the corresponding filter. The DC blocking filter eliminates the DC component in an incoming signal. The frequency response of the DC blocking filter is shown in Figure 1 for the 1X, 2X, and 4X modes.
B ehaviour of D C Filter in Various Modes 10
S pectrum of D e-emphasis Filter 2 32 kHz 44.1 kHz 48 kHz
0
0
-2
-10
A ttenuation in dB
1x mode 2x mode 4x mode
-2 -1 0 1 2
A ttenuation in dB
-4
-20
-6
-30
-8
-40
-10
-50 10
-12 10
10
10 Frequency in Hz
10
10
2
10
3
10 Frequency in Hz
4
10
5
Figure 1. DC Blocking Filter Characteristics
Figure 2. De-Emphasis Filter Characteristics
The De-Emphasis filter is used to re-shape the frequency response and reduce gain for frequencies above 3.183 kHz. It is only available in the 1X mode. If enabled, it needs to be selected for 1 of 4 possible input data rates (32 kHz, 44.1kHz, or 48 kHz), as specified by bits D4 and D3 in the Sampling Rate and DeEmphasis Control Register (address 22h). The frequency response of the De-emphasis filter is shown in Figure 2 for all 3 input data rates. The De-Emphasis Filter Selection bit is ignored for the 2X and 4X input data-sampling modes. A Droop correction filter is included in the TCD6000 to correct for droop and ripple in the frequency response of the entire signal processing chain. The frequency response of the droop filter for the 1X, 2X, and 4X sampling modes is shown below.
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Total Effective D roop, After C orrection 0.5 0.4 0.3 0.2 0.1 1x mode 2x mode 4x mode
db
0 -0.1 -0.2 -0.3 -0.4 -0.5
0
2
4 6 Frequency in kHz
8
10 x 10
4
Figure 3. Frequency response of the Droop Correction Filter Sampling Rate Control
Addr 22h Register Name Sampling Rate Control Default D7 0 0 D6 0 0 D5 0 0 D4 1Xf 0 D3 1Xs 0 D2 0 0 D1 S4X 0 D0 S2X 0
This register allows the user to specify the data-sampling rate (1X, 2X or 4X). When the 1X mode is selected and the de-emphasis filter is enabled, 1Xf and 1Xs select between 32 kHz, 44.1kHz, and 48 kHz deemphasis filters. Bits S4X 0 0 1 Bits 1Xf 0 0 1 1 S2X 0 1 0 or 1 1Xs 0 1 0 1 data-sampling rate is 44.1 kHz data-sampling rate is 32 kHz data-sampling rate is 48 kHz not used 1X mode (32 kHz, 44.1 kHz, or 48 kHz) 2X mode (96 kHz) 4X mode (192 kHz)
If the 2X or the 4X modes are selected, the de-emphasis filter is automatically disabled, and the setting of bit D6 in the Filter Bypass Control register (address 21h) will be ignored. Operation Control
Addr 23h Register Name Operation Control Default D7 0 0 D6 1 1 D5 0 0 D4 0 0 D3 HFR 0 D2 0 0 D1 R1 1 D0 R0 1
This register allows the user to specify 2 operational characteristics of the TCD6000: The Sync Reset mode (control bits R0 and R1) The High Frequency Master Clock option (control bit HFR)
If the Left/Right channel clock (LRCK) and Bit clock (BITCK) are not properly synchronized with the Master clock (MCK) and R0 is set to `1', a "Sync Reset" is generated. If R1 is also set to `1' a hard mute is issued during the Sync Reset and released after the Sync Reset is released.
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During a Sync Reset the DATAnn inputs are ignored and digital silence is substituted. The TCD6000 waits for the clocks to be synchronized before coming out of reset. During Sync Reset, the internal automatic DC offset calibration values are cleared. When the clocks are restored, the system will need to be re-calibrated by hard muting and un-muting or by forcing a DC calibration value in the Calibration Bank. The Sync Reset is different from an external reset, which is created by pulling the RESETB pin low. A Sync Reset will not change the values of I2C addressable read/write registers. R1 enables a "Hard-mute" upon Sync Reset. When the Sync Reset condition is removed, an auto-calibration will take place before the outputs are restored. R0 must be set to `1' for R1 to have any effect. The Master Clock (MCK) input frequency is determined by a combination of the S4X, S2X, and HFR bits and the sampling frequency. The phase of MCK is not critical, as long as the frequency is correctly set. When the HFR bit (register 23h, bit D3) is set to `1', the TCD6000 divides MCK by 2 so that higher frequency system clocks may be used. The duty cycle of MCK should be between 48% and 52% unless HFR is set to `1'. In this case, the division automatically creates a 50% duty cycle internal clock.
HFR 0 0 0 0 1 1 1 1 S4X 0 0 1 1 0 0 1 1 S2X 0 1 0 1 0 1 0 1 MCK pulses per sample 256 128 64 64 512 256 128 128
The following table shows some examples of the MCK clock frequency based on sampling rate and HFR:
Data sampling rate MCK frequency (HFR = `0') MCK frequency (HFR = `1') 32 kHz 8.192 MHz 16.384 MHz 44.1 kHz 11.289 MHz 22.578 MHz 48 kHz 12.288 MHz 24.576 MHz 96 kHz 12.288 MHz 24.576 MHz 192 kHz 12.288 MHz 24.576 MHz
Digital Input Format
Addr 24h Register Name Digital Input Format Default D7 0 0 D6 DP 0 D5 BCK 1 D4 CCK 0 D3 I2S 0 D2 LRA 0 D1 DW1 1 D0 DW0 1
This register allows the user to specify the following digital interface characteristics: Input data width (DW0 and DW1) Input data alignment with respect to LRCK clock edges (LRA) Polarity of the LRCK clock (CCK) Polarity of the BITCK clock (BCK) Polarity of the input data (DP)
The TCD6000 receives PCM digital audio data in I2S format or variations thereof. The format consists of an audio data input (DATAnn), a bit clock (BITCK) that runs at 64x the sampling frequency, and a 1x sampling frequency clock (LRCK). In addition, a master clock (MCK) synchronizes all digital operations inside the device. Each DATAnn input carries serial data for 2 channels. The LRCK clock differentiates between odd
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and even channel data. BITCK is synchronized with the serial data input, and latches data on either rising edges or falling edges of BITCK (programmable option). The TCD6000 has 3 serial data inputs (DATA12, DATA34, and DATA56) and therefore can receive 6 channels of audio data. The group of bits received on a DATAnn input during a half period of LRCK clock is called a PCM data sample. It is a 2's complement representation of the amplitude of sound on that channel at that time. There are 32 pulses of BITCK for every half period of LRCK. So, in theory, it is possible to read up to 32 bits of data per sample. However, only a maximum of 24 bits are read. The device will also accept 16, 18, and 20 bit formats depending on what has been specified in the control registers. The most significant bit of data always arrives first and the least significant bit last. Data can be left aligned or right aligned to the LRCK clock. If data is left aligned, the most significant bit of data arrives at the beginning of the LRCK half-period. If data is right aligned, the least significant bit of data arrives just before the end of the LRCK half-period. DW1 and DW0 define the input data width. Any data outside of the selected data width will be ignored. DW1 0 0 1 1 DW0 0 1 0 1 Input Data Width 16 bit 18 bit 20 bit 24 bit
LRA specifies the left/right data alignment scheme. When LRA is `0', data is left aligned to LRCK transitions. When LRA is `1', data is right aligned to LRCK transitions. If data is left aligned, the most significant bit of data can arrive on the first or the second BITCK pulse. The I2S format specifies that it arrive on the second BITCK pulse. When the I2S control bit is `1', the data conforms to the I2S standard - the most significant data bit is read during the second BITCK pulse. When the I2S control bit is `0', the most significant data bit is read during the first BITCK pulse. If data is right aligned, the I2S control bit has no effect. When CCK is `0', even channel data (channels 2, 4, and 6) is read while LRCK is high and odd channel data (channels 1, 3, and 5) is read while LRCK is low. When CCK is `1', odd channel data is read while LRCK is high and even channel data is read while LRCK is low. When BCK is `1', data is latched on the falling edge of BITCK. When BCK is `0', data is latched on the rising edge of BITCK. DP is used to specify the polarity of the 2's complement audio data. If DP is `0', the data is non-inverted. If DP is `1', the data is inverted. Figure 1 shows several examples of digital input format. Notice that for a given stereo audio sample, the TCD6000 reads even channels first and then the odd channels. I2S and most of its variations first send left channel data and then right channel data within stereo audio sample frames. Therefore, the TCD6000 sends left channel input data to output channels 2, 4 and 6 and right channel input data to output channels 1, 3, and 5. Inverting CCK to send left channel data to odd channels can potentially cause phase shift problems. For example, if standard I2S data is received with register 24h = 0Bh instead of 1Bh, stereo data frames are read beginning with the rising edge of LRCK instead of the falling edge. This means that left and right channel data will be out of phase by 1/2 of a LRCK cycle.
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REG 24h TEST DP BCK CCK I2S LRA DW 1 DW 0 STEREO AUDIO SAMPLE LRCK BITCK DATAnn MSB 24 Bits LSB 8 Bits MSB 24 Bits LSB 8 Bits ch 2, 4, 6 ch 1, 3, 5
00000011
00010011
LRCK BITCK DATAnn MSB
ch 2, 4, 6
ch 1, 3, 5
LSB 24 Bits 8 Bits
MSB 24 Bits
LSB 8 Bits
00011011
LRCK BITCK DATAnn MSB
ch 2, 4, 6
ch 1, 3, 5
LSB 24 Bits 7 Bits
MSB 24 Bits
LSB 7 Bits
00001011
LRCK BITCK DATAnn MSB
ch 2, 4, 6
ch 1, 3, 5
LSB 24 Bits 7 Bits
MSB 24 Bits
LSB 7 Bits
00000100
LRCK BITCK DATAnn LSB 16 Bits
ch 2, 4, 6
ch 1, 3, 5
MSB 16 Bits
LSB 16 Bits
MSB 16 Bits
LSB
0000
0
101
LRCK BITCK DATAnn LSB 14 Bits
ch 2, 4, 6
ch 1, 3, 5
MSB 18 Bits
LSB 14 Bits
MSB 18 Bits
LSB
00000110
LRCK BITCK DATAnn LSB 12 Bits
ch 2, 4, 6
ch 1, 3, 5
MSB 20 Bits
LSB 12 Bits
MSB 20 Bits
LSB
00000111
LRCK BITCK DATAnn LSB 8 Bits
ch 2, 4, 6
ch 1, 3, 5
MSB 24 Bits
LSB 8 Bits
MSB 24 Bits
LSB
Figure 1 Digital Audio Input Formats 20 TCD6000 - Rev. 1.0/09.04
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Channel Volume
Addr 25h 26h 27h 28h 29h 2Ah Register Name Channel 1 Volume Channel 2 Volume Channel 3 Volume Channel 4 Volume Channel 5 Volume Channel 6 Volume Default D7 V17 V27 V37 V47 V57 V67 0 D6 V16 V26 V36 V46 V56 V66 0 D5 V15 V25 V35 V45 V55 V65 0 D4 V14 V24 V34 V44 V54 V64 0 D3 V13 V23 V33 V43 V53 V63 0 D2 V12 V22 V32 V42 V52 V62 0 D1 V11 V21 V31 V41 V51 V61 0 D0 V10 V20 V30 V40 V50 V60 0
The TCD6000 has 6 channel volume registers, one for each channel. The 8-bit value in each register represents the volume loudness for the corresponding channel. The least significant bit, D0, represents a volume increment of 0.5dB. Therefore the total range available is 128dB. Maximum volume is achieved when the volume register contains a value of FFh, and no sound is heard if its value is 00h. In addition, a "coarse gain" adjustment (1X, 2X, 4X, and 8X) is made possible by programming the Volume Change Control Register. Volume Ramp Rate
Addr 2Bh Register Name Volume Ramp Rate Default D7 RR7 1 D6 RR6 0 D5 RR5 0 D4 RR4 0 D3 RR3 0 D2 RR2 0 D1 RR1 0 D0 RR0 0
The TCD6000 can be programmed to have volume changes take effect immediately or be ramped at a predefined rate for all channels. If the Volume Ramp Enable bit is set, the Volume Ramp Rate Register defines the ramp rate. Although the Volume Control Registers define the channel volume within an accuracy of 1/2 dB, volume will be ramped internally in 1/8 dB steps when ramping is enabled. The number entered into the Volume Ramp Rate Register can be from 0 (00h) to 255 (FFh). If the number entered is N, the time delay between two consecutive 1/8 dB volume increments is equal to: N x (4 periods of LRCK) As an example, if N = 100 and data samples are coming in at a 44.1kHz rate, the period of LRCK is 22.67usec. The delay between two consecutive 1/8 dB volume increments is: 100 x 4 x 22.67usec = 9068usec Therefore if the volume change is 60 dB (480 increments of 1/8 dB), the total ramp time will be: 480 x 9068usec = 4.32 second Channel Mute Control
Addr 2Ch Register Name Channel Mute Control Default D7 M6 0 D6 M5 0 D5 M4 0 D4 M3 0 D3 M2 0 D2 M1 0 D1 HM 1 D0 AM 0
The TCD6000 has 3 different Mute functions: Soft-Mute, Hard-Mute, and Auto-Mute.
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The Soft-Mute function will turn off volume selectively on any of the 6 channels. Setting control bits M1 through M6 to `1' will issue a Soft-Mute on the corresponding channels. If the VRE bit in the Volume Change Control Register is set, the volume will first ramp down at a rate defined by the Volume Ramp Rate Register. Soft-Mute has no affect on whether the differential outputs (Y1 and Y1B through Y6 and Y6B) continue to switch or not. Clearing bits M1 through M6 to `0' will re-establish volume on all channels at a rate defined by the Volume Ramp Enable settings. The Hard-Mute function is enabled by setting control bit HM high. This function starts with a Soft-Mute on all channels simultaneously. If the VRE bit in the Volume Change Control Register is set, the volume will first ramp down at a rate defined by the Volume Ramp Rate Register. Once volume is turned off on all channels, all differential outputs (Y1 and Y1B through Y6 and Y6B) stop switching. This will reduce power consumption in the power stages driven by the TCD6000. When control bit HM is cleared to `0', the Hard-Mute condition is removed, and the TCD6000 goes through an automatic DC calibration cycle. Once the calibration cycle is complete, volume is re-established on all channels at a rate defined by the Volume Ramp Enable settings. The Auto-Mute function is enabled by setting the AM bit to `1'. This function detects digital silence (all data input bits at 0) on all 6 channels lasting more than a pre-defined delay. It then issues a Hard-Mute. The delay is determined by the contents of the Auto-Mute Timing Register (described below). Upon arrival of non-zero data on any channel, the Hard-Mute condition is automatically removed. The volume on all 6 channels is re-established at a rate defined by the Volume Ramp Enable settings. The Auto-Mute function reduces power consumption in the power stages during periods of silence. Auto-Mute Timing
Addr 2Dh Register Name Auto-Mute Timing Default D7 AM7 0 D6 AM6 0 D5 AM5 0 D4 AM4 0 D3 AM3 0 D2 AM2 0 D1 AM1 0 D0 AM0 0
This register is only used if the Auto-Mute function is enabled. Its contents specify the duration of silence on all 6 channels before a Hard-Mute condition is issued. If the number entered is "N", the duration of silence is equal to: (2N + 1) x (1,048,576 periods of LRCK) As an example, if N = 1 and the period of LRCK is 22.67usec, the period of silence required before a HardMute condition is issued is: 3 x 1,048,576 x 22.67usec = 71.3 seconds
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Volume Change Control
Addr 2Eh Register Name Volume Change Control Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 VR1 0 D2 VR0 1 D1 VRE 0 D0 ZCE 0
This register is used to specify 3 characteristics of volume change for all channels: Coarse Gain (control bits VR0 and VR1) Volume Ramp Enable (control bit VRE) Zero-Crossing Enable (control bit ZCE)
Coarse Gain is a simple volume adjustment made by shifting bits to the left. Coarse Gain is set by selecting one of four combinations for bits VR0 and VR1. Coarse Gain affects all 6 channels globally. Coarse Gain can cause premature digital clipping when used with PGC because internal digital gain approaches maximum at each PGC boundary. Therefore when using PGC, Coarse Gain should not be enabled until maximum volume has been reached on all channels. Bits VR1 0 0 1 1 VR0 0 1 0 1 1X volume 2X volume 4X volume 8X volume
The VRE control bit is the Volume Ramp Enable bit. If VRE = `1', the contents of the Volume Ramp Rate Register will be read and determine how fast the volume can ramp up or down on all 6 channels. Refer to the Volume Ramp Rate Register section for a more detailed explanation of how the ramp rate is calculated. The ZCE control bit is the Zero-Crossing Enable bit. A polarity inversion on the audio input signal is called a "Zero-Crossing". Changing volume only at Zero-Crossings helps to avoid popping sounds. If ZCE is set to `1', volume will only be allowed to change at Zero-Crossings. However, if a Zero-Crossing does not occur within a time defined by the Volume Ramp Rate Register (called "time-out" in the graph below), volume will change anyway. If the Zero-Crossing feature is enabled, the VRE control bit will still control whether the volume change occurs in one large step or in 1/8 dB steps at Zero-Crossings.
Amplitude
Volume change occurs at every zero-crossing
Audio signal
Time
No zero-crossing, volume change occurs after time-out time-out
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Volume Change Flowchart
Volum e change requested
VRE = 1 ?
No
Yes
ZCE = 1 ?
No
ZCE = 1 ?
No
Yes
Yes
W ait for zero crossing or tim eout (whichever com es first)
W ait for tim eout
W ait for zero crossing or tim eout (whichever com es first)
W ait for tim eout
Change volum e by 1/8 dB
Change volum e to desired setting
No
Reached desired setting?
End
Yes
End
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Automatic DC Offset Calibration Control
Addr 2Fh Register Name Automatic DC Calibration Control Default D7 0 0 D6 CAB 0 D5 CF6 0 D4 CF5 0 D3 CF4 0 D2 CF3 0 D1 CF2 0 D0 CF1 0
The CFn bits control which DC offset calibration values will be used. If a particular channel's CFn bit is set to `1', the value stored in the Calibration Bank registers will be used. If CFn is cleared to `0', the Automatic DC Offset Calibration values that were calculated after coming out of hard mute will be used. Setting the CAB bit to `1' will bypass Automatic DC Offset Calibration. Calibration Bank
Addr 30h 31h 32h 33h 34h 35h 36h 37h Register Name Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Calibration Bank Default D7 CB19 CB29 CB39 0 CB49 CB59 CB69 0 0 D6 CB18 CB28 CB38 0 CB48 CB58 CB68 0 0 D5 CB17 CB27 CB37 CB31 CB47 CB57 CB67 CB61 0 D4 CB16 CB26 CB36 CB30 CB46 CB56 CB66 CB60 0 D3 CB15 CB25 CB35 CB21 CB45 CB55 CB65 CB51 0 D2 CB14 CB24 CB34 CB20 CB44 CB54 CB64 CB50 0 D1 CB13 CB23 CB33 CB11 CB43 CB53 CB63 CB41 0 D0 CR12 CR22 CR32 CR10 CR42 CR52 CR62 CR40 0
These registers store calibration values that can be forced instead of the automatic DC calibration values. Register 2Fh controls whether the automatic values will be used or the Calibration Bank values. The DC calibration values are 10 bit words so they are stored in separate bytes. For example, for channel 1, the 8 most significant bits are stored in register 30h, while the 2 least significant bits are stored in register 05h - bits D1 and D0. Force DC
Addr 38h Register Name Force DC Default D7 FD7 0 D6 FD6 0 D5 FD5 0 D4 FD4 1 D3 FD3 1 D2 FD2 1 D1 FD1 0 D0 FD0 0
This register is used to force a DC offset in the system. It is used for testing purposes. It should be changed from its default setting to 00h for normal operation. Dither Control
Addr 39h Register Name Dither Control Default D7 DT7 0 D6 DT6 0 D5 DT5 0 D4 DT4 0 D3 DT3 0 D2 DT2 0 D1 DT1 0 D0 DT0 0
This register is used to set the amount of dither in the system. It should be set to 3Ch for normal operation.
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Fault Latch Control
Addr 3Ah Register Name Fault Latch Control Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 FLD 1 D1 FLC 0 D0 0 0
FLD and FLC control the TCD6000 behavior after FAULT has been asserted. If FLD is set to `1', the TCD6000 will automatically un-mute after FAULT is released (floated). If FLD is cleared to `0', the TCD6000 will remain latched in this FAULT-based muted condition until the FAULT pin is released and FLC undergoes a `0' to `1' transition. Saturation Clamp
Addr 3Bh 3Ch Register Name Saturation Clamp LSB Saturation Clamp MSB D7 1 1 D6 1 1 D5 1 1 D4 1 0 D3 1 0 D2 1 1 D1 1 1 D0 1 1
The Saturation Clamp is a 16 bit word that determines the internal digital saturation point. It should be set to E7FFh for the maximum range of operation. Predictive Gain Control
Addr 3Dh Register Name Predictive Gain Control Default D7 PGC 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
Predictive Gain Control is enabled when PGC is set to `1'. It is disabled when PGC is cleared to `0'. PGC should not be turned on or off while not in hard-mute. Doing so will have unpredictable results.
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Output Delay Control
Addr 73h Register Name Output Delay Control Default D7 0 0 D6 0 0 D5 YSGL 0 D4 0 0 D3 YD3 0 D2 YD2 0 D1 YD1 0 D0 YD0 0
During automatic DC calibration the TCD6000 expects to be able to turn off both the high and low side FETs by pulling Y and Yb low. However, some power stages like the TRIPATH TPD2075 and TPD2125 only have a single Y input instead of complimentary Y and Yb inputs. When using this type of power stage, YSGL should be cleared to `1'. Then, during automatic DC calibration, HPO should be set to `1'. This keeps the HMUTE output high during automatic DC calibration. After waiting for automatic DC calibration to complete, HPO can be set to `0' to resume normal switching. When using other power stages, YSGL can be kept at `0'. The YDn bits control the loop delay of the Class-T amplification channels. This can be used to control the maximum output switching frequency. Each channel receives the same amount of additional delay which defaults to 15nS but can be increased from 15nS to 240nS in 15nS steps.
YD<3:0> 0000 (POR default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Actual count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Processor Y-output delay 15 nS 30 nS 45 nS 60 nS 75 nS 90 nS 105 nS 120 nS 135 nS 150 nS 165 nS 180 nS 195 nS 210 nS 225 nS 240 nS
Truth table for Y-output delay control. Headphone and Logic Output Control
Addr 74h Register Name Headphone and Logic Output Default D7 0 0 D6 HMP 0 D5 HPO 0 D4 TO 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0
Setting the TO control bit to `1' forces the TST_EN output pin to go high. This pin can be used to put the power stage IC into test mode. If the power stage does not have a TST_EN input, the TST_EN output can be used as a general purpose logic output. The HPO control bit immediately stops all switching without muting the headphone amplifier outputs. The HMP bit controls whether the HMUTE output is active high or active low. Setting HMP to `1' causes the HMUTE output to be active low.
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Output Timing Control
Addr 76h Register Name Output Timing Control Default D7 DEL 0 D6 DCB 0 D5 0 0 D4 0 0 D3 STB 0 D2 BB2 0 D1 BB1 0 D0 BB0 0
Control bits BB0 through BB2 are used to program a "break before make" delay in the Y outputs. Break before make is a dead time at the Y-outputs where both Y and YB of each channel are low together for a period of time in order to prevent shoot-through current in the output power MOSFET devices. . BB<2:0> 000 001 010 011 100 101 110 111 BBM Delay 0 nS 15 nS 30 nS 45 nS 60 nS 75 nS 90 nS 105 nS Break before make (BBM) delay table The STB control bit enables a 16-bit Startup Burst for driving bootstrapped output stages. The DCB control bit controls the method of automatic DC calibration that will be used. DCB should be set to `1' if a bridged output stage is being used. DCB should be cleared to `0' if a single ended output stage is being used. The BCn bits work in conjunction with the DCB bit. When DCB is set to '1', the BCn bits should be set to '1'. When DCB is cleared to '0', the BCn bits should be cleared to '0'. The DEL control bit enables the on-chip delay compensation. Delay compensation corrects for loop instability that can be caused by propagation delay through power stages. It should always be set to `1'. Individual Hard Mute Control
Addr 77h Register Name Individual Hard Mute Control Default D7 0 0 D6 HM6 0 D5 HM5 0 D4 HM4 0 D3 HM3 0 D2 HM2 0 D1 HM1 0 D0 0 0
Setting an HMn bit to `1' stops switching on an individual output channel. Clearing the bit to `0' resumes normal operation. Post-Gain Control
Addr 78h Register Name Post Gain Control Default 7Ah Post Gain Control Default 7Bh Post Gain Control Default D7 GN1 0 GN2 0 GN6 0 D6 0 0 0 0 GN5 0 D5 0 0 0 0 GN4 0 D4 0 0 0 0 GN3 0 D3 0 0 0 0 0 0 D2 0 0 0 0 0 0 D1 0 0 0 0 0 0 D0 0 0 0 0 0 0
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When the GNn control bits are cleared to `0', the TCD6000 operates in low post-gain mode. In this mode, the noise floor is lowered but the system may not be able to obtain the maximum power output from the power stage. When the GNn control bits are set to `1', the TCD6000 operates in high post-gain mode. In this mode, gain is increased by 25%. The system will now be able to obtain the maximum power output from the power stage but the noise floor will have increased accordingly. B Cal Control
Addr 7Dh Register Name Force Offset and B Cal Control Default D7 0 0 D6 BC6 0 D5 BC5 0 D4 BC4 0 D3 BC3 0 D2 BC2 0 D1 BC1 0 D0 0 0
The BCn control bits control the method of automatic DC calibration that will be used. The BCn bits should be set to `1' if a bridged output stage is being used. The BCn bits should be cleared to `0' if a single ended output stage is being used. The BCn bits work in conjunction with the DCB bit. When DCB is set to '1', the BCn bits should be set to '1'. When DCB is cleared to '0', the BCn bits should be cleared to '0'.
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I2C Programming Examples
Initialization string for a TRIPATH TP2150B with PGC off: sub-address value 20h 00000000b Un-freeze registers. System starts in mute so the instruction sequence is not important. 21h 11000000b Turn off de-emphasis and DC blocking filters. Turn on droop correction filter. 22h 00010000b 48kHz sampling rate. 23h 01000011b MCK will be 48kHz * 256 = 12.288MHz. Sync Reset is on and it will trigger a hard-mute. 24h 00011011b Standard I2S format. 25h 00h Channel 1 Volume 26h 00h Channel 2 Volume 27h 00h Channel 3 Volume 28h 00h Channel 4 Volume 29h 00h Channel HP1 Volume 2Ah 00h Channel HP2 Volume 2Bh 00h Leave Volume Ramp Rate at 00h while not changing volume. 2Ch 00000010b Start out in hard-mute. Turn off Auto-Mute. 2Dh 00h Auto-Mute Timing 2Eh 00000011b Coarse Gain = 1x. Volume Ramp Enable and Zero Crossing Enable 2Fh 01100000b Bypass DC calibration for headphone outputs. 30h 00h CalibBank0Ex 31h 00h CalibBank1Ex 32h 00h CalibBank2Ex 33h 00h CalibBank012Ex 34h 00h CalibBank3Ex 35h 00h CalibBank4Ex 36h 00h CalibBank5Ex 37h 00h CalibBank345Ex 38h 00h Clear Force DC register. 39h 3Ch Set Dither Control to 3Ch. 3Ah 00000100b Enable Fault Latch. 3Bh FFh Always set Saturation Clamp to these values. 3Ch E7h Always set Saturation Clamp to these values. 3Dh 00000000b Turn on PGC. 73h 00001011b Use 195nS delay to slow down switching (adjust as needed for each design). 74h 00000000b HMUTE is active high, HPO = 0, TST_EN output is low. 75h 00h Test. 76h 10001011b Enable Delay compensation. Use A-cal for single ended output. Enable startup burst for bootstrap. BBM = 45nS (adjust as needed for each design). 77h 00000000b Individual channel hard mutes are inactive. 78h 10000000b Channel 1 high post-gain. 79h 00h Test. 7Ah 10000000b Channel 2 high post-gain. 7Bh 11110000b Channel 3, 4, 5, and 6 high post-gain. 7Ch 00h Test. 7Dh 00000000b All channels use A-cal for single ended output.
To Un-mute a TP2150B: sub-address value 2Ch 00000000b Remove Hard-Mute to begin automatic DC calibration.
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OUTPUT CHARACTERISTICS The TCD6000 outputs consist of six pairs of complementary 1-bit digital data streams, one pair per audio channel. They switch from 0V to 5V (+/- 10%) and constitute a pulse-density-modulated (PDM) form of the audio signal. They are used to drive TRIPATH power stages in a switching amplifier configuration.
2 The output power of a power stage can be expressed as V /R, V being the voltage amplitude of the power stage output and R the speaker input impedance, typically 4 to 8 ohms.
The audio signal is recovered by filtering the PDM signal through an LC filter located at the inputs of the speaker. The following figure shows the power stage output waveform and the filtered signal at the speaker inputs:
Typical waveform at power stage output
Typical waveform at speaker inputs after LC filtering
TCD6000 outputs are pulse density modulated outputs. Their frequency varies constantly over time and can typically reach a maximum value of 800 kHz. A Mute output (HMUTE) can be connected to all 6 power stages to force them into a tri-state mode when a hard mute condition is encountered. The HMUTE output can be programmed to be either active-high or active-low (bit D6 in control register 74h). An overload is detected whenever the combination of input signal amplitude and volume programmed in the TCD6000 results in output signal saturation and distortion. The OVRLDB pin goes active low when this condition occurs. A test output pin is also provided (TST_EN) for external testing purposes. Setting bit D4 in control register 74h will force this output to an active high state. The HMUTE, OVRLDB and TST_EN outputs are 5V digital outputs. The TCD6000 also includes a pair of stereo headphone outputs (HP1 and HP2), which are connected to channels 1 and 2. These outputs are analog with maximum 3V peak-to-peak amplitude. They have a common mode voltage of 2V and should therefore be AC coupled to the headphone jack. If the headphone outputs are not being used, these pins may be left unconnected.
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FEEDBACK CONNECTIONS
V+ Y
LC filter
TCD6000
YB
L C
FBN
FBP R1
5V R1 R3 R3
V-
R2
R2
Figure 2 - Feedback network for single ended configurations (1 channel shown) Differential feedback from the power stage outputs to the TCD6000 FB inputs is required. This feedback is taken directly from the outputs of the power stage, before the LC filter stage. It allows the TCD6000 to compensate for power stage distortion (non-linearity, power supply noise, etc.) and to deliver an ultra-low THD that is unique to class-T technology. Total harmonic distortion is typically less than 0.03% with most power stages. Resistors R1, R2, and R3 create a voltage divider structure to reduce the unfiltered output of the power stage for the feedback pins. In single ended output configurations like the one shown in Figure 2, the feedback voltage should be approximately 4Vpp. R1 and R2 bias the feedback signal to approximately 2.5V and R3 scales the large output voltages down to 4Vpp. The input impedance of the TCD6000 feedback pins is approximately 25K. To solve for the values of the feedback resistors in a single ended configuration:
R1 = User specified, typically 1K R2 = R1 * VPP VPP * R1 (VPP - 4 ) 25K R1 * VPP 4
R3 =
The above equations assume that VPP = |VNN|. For example, in a system with VPPMAX = +28V and VNNMAX = -28V, R1 = 1k, 1% R2 = 1.224k, use 1.21k, 1% R3 = 7.00k, use 6.98k, 1%
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V+ Y
LC filter
L C
TCD6000
Power Stage
V+
LC filter
L YB C
FBN
FBP
R3 R3
R2
R2
Figure 3 - Feedback network for bridged configurations (1 channel shown) In bridged configurations like the one shown in Figure 3, R1 is absent (infinity). Since the feedback is now bridged, the feedback voltage should be cut in half to 2Vpp. To solve for the values of the feedback resistors in a bridged configuration:
R2 = User specified, typically 1K 25K * R2 VPP - 2 * 25 K + R 2 2
R3 =
For example, in a system with VPPMAX=30V, R2 = 1k, 1% R3 = 13.462k, use 13.3k, 1%
VCLAMP PIN BIASING The VCLAMP pin must have a DC voltage applied which is proportional to the peak to peak voltage swing of the power output switching stage in the amplifier system. More explicitly, the potential at VCLAMP should be 0.525 times the peak to peak differential voltage seen at each channel's feedback pins (i.e., the full final value voltage swing neglecting any RC settling time effects). This means that the component values used in the circuitry biasing the VCLAMP pin are a direct function of the chosen feedback network components. In a full bridged system, proper VCLAMP biasing is achieved via a simple two resistor divider between V+ (the output stage power supply) and ground, shown in the right-hand portion of the circuit below (excluding the portion in the dotted line box). In a single ended (half bridge) system, VCLAMP biasing is achieved by the entire six element circuit below.
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. Figure 4 - VCLAMP biasing In a bridged system, stated in terms of the components described in the feedback section, the values for Ra and Rb are determined as follows (Rd = 0.176 x Ra):
0.952 x R3 Ra = Rb x R2 || 25K - 0.048
where R2||25k is the parallel combination of R2 and 25k Ohms. In a single ended (half bridge) system, the component value relationships would be, stated in terms of the components in the feedback section:
1.90 x R3 Ra = Rb x R1 || R2 || 25K + 0.90
where Rd = 0.176 x Ra, and R1||R2||25k is the parallel combination of R1, R2, and 25k Ohms.
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Package Information (QFP 100)
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PRELIMINARY - This product is still in development. TRIPATH Technology Inc. reserves the right make any changes without further notice to improve reliability, function or design. This data sheet contains the design specifications for a product in development. Specifications may change in any manner without notice. TRIPATH and Digital Power Processing are trademarks of TRIPATH Technology Inc. Other trademarks referenced in this document are owned by their respective companies. TRIPATH Technology Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. TRIPATH does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. TRIPATH'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Contact Information
TRIPATH TECHNOLOGY, INC
2560 Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.TRIPATH.com/cont_s.htm For more Technical Information, please visit us @ www.TRIPATH.com/data.htm
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